{"id":21006,"date":"2015-11-30T13:29:22","date_gmt":"2015-11-30T12:29:22","guid":{"rendered":"https:\/\/www.inovex.de\/\/?p=1169"},"modified":"2025-03-24T07:38:53","modified_gmt":"2025-03-24T06:38:53","slug":"enhancing-a-device-tree-for-arm-cpus","status":"publish","type":"post","link":"https:\/\/www.inovex.de\/de\/blog\/enhancing-a-device-tree-for-arm-cpus\/","title":{"rendered":"Enhancing a Device Tree for ARM CPUs"},"content":{"rendered":"<p>Traditionally, the specific hardware configurations are described in so called board-description files and permanently embedded into the kernel during compilation, making it necessary to re-compile the kernel to change pin assignment.\u00a0The Device Tree is supposed to revolutionize that\u00a0by\u00a0reading the hardware configuration from a data structure stored in RAM at startup. In this article we describe how to enhance\u00a0the Device Tree to support additional hardware.<!--more--><\/p>\n<div id=\"ez-toc-container\" class=\"ez-toc-v2_0_79_2 counter-hierarchy ez-toc-counter ez-toc-custom ez-toc-container-direction\">\n<div class=\"ez-toc-title-container\"><p class=\"ez-toc-title\" style=\"cursor:inherit\"><\/p>\n<\/div><nav><ul class='ez-toc-list ez-toc-list-level-1 ' ><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-1\" href=\"https:\/\/www.inovex.de\/de\/blog\/enhancing-a-device-tree-for-arm-cpus\/#What-the-%C2%A7-is-a-Device-Tree\" >What the *#+\/%\u00a7* is a Device Tree?<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-2\" href=\"https:\/\/www.inovex.de\/de\/blog\/enhancing-a-device-tree-for-arm-cpus\/#Adding-GPIO-to-a-Pandaboard-%E2%80%93-Hands-On\" >Adding GPIO to a\u00a0Pandaboard \u2013 Hands On<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-3\" href=\"https:\/\/www.inovex.de\/de\/blog\/enhancing-a-device-tree-for-arm-cpus\/#Sources\" >Sources<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-4\" href=\"https:\/\/www.inovex.de\/de\/blog\/enhancing-a-device-tree-for-arm-cpus\/#Get-in-Touch\" >Get in Touch<\/a><\/li><\/ul><\/nav><\/div>\n<h2><span class=\"ez-toc-section\" id=\"What-the-%C2%A7-is-a-Device-Tree\"><\/span>What the *#+\/%\u00a7* is a Device Tree?<span class=\"ez-toc-section-end\"><\/span><\/h2>\n<p>Embedded systems usually rely on ARM based CPUs, as they provide better power efficiency and modifiability than other architectures. ARM itself just sells licenses for their architectures that allow other manufacturers to modify the chip designs, e.g. by adding hardware interfaces. Unified interfaces such as defined addresses and interrupts are not available.<\/p>\n<p>Accordingly each ARM-platform comes with its own drivers and modules. That\u2019s why it is not possible to run one kernel on different ARM Systems-on-a-Chip (SoC) and development boards.<\/p>\n<p>Traditionally, the specific hardware configurations are described in so called board-description files and permanently embedded into the kernel during compilation. Kernel sources are then expanded according to the number of files needed. Furthermore modern ARM architectures use pins for multiple purposes. With multiplexing, a pin may e.g-\u00a0work as GPIO or as part of a I2C or a SPI interface. Thus board files have to be added at compilation time and cannot be modified afterwards. For changing the pin assignment it is necessary to re-compile the kernel.<\/p>\n<p><a href=\"https:\/\/www.inovex.de\/wp-content\/uploads\/2015\/11\/IMG_0018.jpg\"><img loading=\"lazy\" decoding=\"async\" class=\"aligncenter size-medium wp-image-1181\" src=\"https:\/\/www.inovex.de\/wp-content\/uploads\/2015\/11\/IMG_0018-300x200.jpg\" alt=\"IMG_0018\" width=\"300\" height=\"200\" srcset=\"https:\/\/www.inovex.de\/wp-content\/uploads\/2015\/11\/IMG_0018-300x200.jpg 300w, https:\/\/www.inovex.de\/wp-content\/uploads\/2015\/11\/IMG_0018-1024x683.jpg 1024w, https:\/\/www.inovex.de\/wp-content\/uploads\/2015\/11\/IMG_0018-768x512.jpg 768w, https:\/\/www.inovex.de\/wp-content\/uploads\/2015\/11\/IMG_0018-1536x1024.jpg 1536w, https:\/\/www.inovex.de\/wp-content\/uploads\/2015\/11\/IMG_0018-2048x1365.jpg 2048w, https:\/\/www.inovex.de\/wp-content\/uploads\/2015\/11\/IMG_0018-1920x1280.jpg 1920w, https:\/\/www.inovex.de\/wp-content\/uploads\/2015\/11\/IMG_0018-400x267.jpg 400w, https:\/\/www.inovex.de\/wp-content\/uploads\/2015\/11\/IMG_0018-360x240.jpg 360w\" sizes=\"auto, (max-width: 300px) 100vw, 300px\" \/><\/a><\/p>\n<p>The Device Tree is supposed to revolutionize this. Its idea is to read the hardware configuration from a data structure stored in RAM at startup. So it is possible to run one kernel on multiple development boards, just by swapping the data structure\u2014a technique formerly used for the Power-PC.<\/p>\n<p>With device tree overlays, kernel developers create a mechanism to configure a board\u2019s pins at run time from within the userspace.<\/p>\n<p>Device Tree descriptions are located in <span class=\"lang:sh decode:true crayon-inline\">arch\/arm\/boot\/dts<\/span>. While files named <span class=\"lang:sh decode:true crayon-inline \">.dtsi<\/span>\u00a0 contain base definitions for a defined SoC, files ending in <span class=\"lang:sh decode:true crayon-inline \">.dts<\/span>\u00a0 describe individual boards.<\/p>\n<p>The Device Tree Compiler (DTC) compiles the files to binary blobs called Device Tree Blobs (DTB) with the command<span style=\"font-weight: 400;\"> <span class=\"lang:sh decode:true crayon-inline \">make dtbs<\/span><\/span>. There is a specific blob for each device like <span class=\"lang:sh decode:true crayon-inline \">omap4-panda-es.dtb<\/span> for a Pandaboard ES with an OMAP4 ARM CPU.<\/p>\n<p>The bootloader, for most embedded devices U-Boot, loads the DTB into the RAM along with the Kernel and the root file system. At startup the kernel gets informed about its hardware configuration by the DTB.<\/p>\n<h2><span class=\"ez-toc-section\" id=\"Adding-GPIO-to-a-Pandaboard-%E2%80%93-Hands-On\"><\/span>Adding GPIO to a\u00a0Pandaboard \u2013 Hands On<span class=\"ez-toc-section-end\"><\/span><\/h2>\n<p>The Device Tree is a quite new mechanism in the kernel. At the moment there isn\u2019t one yet for every SoC and corresponding development board and those who do exist are quite incomplete.<\/p>\n<p>There is one for the Pandaboard ES\u2014which we want to use as an example\u2014, however there are no definitions for the pins of the expansion headers. Below we will show how to add support for the GPIO function of the board. With pin multiplexing it is quite simple to change the mode of the enabled pins, too, e.g. to parts of an UART interface.<\/p>\n<p>We will start with the memory addresses for the pins with GPIO functionality which can be found in <a href=\"http:\/\/www.ti.com\/lit\/ug\/swpu235ab\/swpu235ab.pdf\"><span style=\"font-weight: 400;\">the CPU&#8217;s Technical Reference Manual<\/span><\/a> (TRM). They are located in the address area 0x4a100000 which is the pinmux core domain. In the device tree structure 0x4a100040 is the base address for this domain. To identify the pins in the structure, offsets are calculated from the core domain address and the representation in the DTS file. For simplicity all relevant information is collected in the table below. At first the original address based on the pinmux core domain is named, then the offset which is used in the device tree.<\/p>\n<p><a href=\"https:\/\/www.inovex.de\/wp-content\/uploads\/2015\/11\/domain-adresses-2.png\"><img decoding=\"async\" src=\"https:\/\/www.inovex.de\/wp-content\/uploads\/2015\/11\/domain-adresses-2-260x300.png\" alt=\"domain-adresses-2\" width=\"260\" \/><\/a> <a href=\"https:\/\/www.inovex.de\/wp-content\/uploads\/2015\/11\/domain-adresses-1.png\"><img decoding=\"async\" src=\"https:\/\/www.inovex.de\/wp-content\/uploads\/2015\/11\/domain-adresses-1-285x300.png\" alt=\"domain-adresses-1\" width=\"260\" \/><\/a><\/p>\n<p>Next we extend the device tree structure in omap4-panda-es.dts. To add support for GPIOs located in the pinmux core domain, the node <span class=\"lang:sh decode:true crayon-inline \">&amp;omap4_pmx_core<\/span>\u00a0 is the right place. For a clean representation each used pin is assigned to its expansion header on the Pandaboard. So <span class=\"lang:sh decode:true crayon-inline \">&amp;omap4_pmx_core<\/span>\u00a0 is expanded with two sub-nodes, <span class=\"lang:sh decode:true crayon-inline \">pinmux_j3_gpios<\/span>\u00a0 and <span class=\"lang:sh decode:true crayon-inline \">pinmux_j6_gpios<\/span>.<\/p>\n<p>Within them, an entry defining a pin starts with the offset to identify the right one. The first constant specifies whether the pin is used as input or output, either of which can be a pull up or a pull down resistor. The second one defines the multiplexing mode. For all considered pins, mode 3 set them to GPIO functionality. The manual lists the functionalities and corresponding modes.<\/p>\n<p>After loading the expanded device tree blob into the kernel, the new added nodes appear in the proc file system under <span class=\"lang:sh decode:true crayon-inline \">\/proc\/device-tree\/ocp\/pinmux@4a100040<\/span>\u00a0and the GPIOs should work.<\/p>\n<pre class=\"lang:c decode:true \">\/* Pinmux for gpios on J3 expansion header *\/\r\n\r\nj3_gpios: pinmux_j3_gpios{\r\n\r\n\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0pinctrl-single,pins =&lt;\r\n\r\n\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a00x1e (PIN_OUTPUT | MUX_MODE3) \u00a0\u00a0\u00a0\/* gpio_39.gpmc_ad15 *\/ \u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\r\n\r\n\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\/\/ 0xee (PIN_OUTPUT | MUX_MODE3) \/* i2c4_scl.gpio_132 used as i2c4 defined in omap4-panda-commom.dtsi *\/\r\n\r\n\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\/\/ 0xf0 (PIN_OUTPUT | MUX_MODE3) \/* i2c4_sda.gpio_133 used as i2c4 defined in omap4-panda-commom.dtsi *\/ \u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\r\n\r\n\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a00xf2 (PIN_OUTPUT | MUX_MODE3) \u00a0\u00a0\u00a0\/* gpio_134.mcspi1_clk *\/\r\n\r\n\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a00xf4 (PIN_OUTPUT | MUX_MODE3) \u00a0\u00a0\u00a0\/* gpio_135.mcspi1_somi *\/\r\n\r\n\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a00xf6 (PIN_OUTPUT | MUX_MODE3) \u00a0\u00a0\u00a0\/* gpio_136.mcspi1_simo *\/\r\n\r\n\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a00xf8 (PIN_OUTPUT | MUX_MODE3) \u00a0\u00a0\u00a0\/* gpio_137.mcspi1_cs0 *\/\r\n\r\n\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a00xfa (PIN_OUTPUT | MUX_MODE3) \u00a0\u00a0\u00a0\/* gpio_138.mcspi1_cs1 *\/\r\n\r\n\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a00xfc (PIN_OUTPUT | MUX_MODE3) \u00a0\u00a0\u00a0\/* gpio_139.mcspi1_cs2 *\/\r\n\r\n\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a00xfe (PIN_OUTPUT | MUX_MODE3) \u00a0\u00a0\u00a0\/* gpio_140.mcspi1_cs3 *\/ \u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\r\n\r\n\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a00x11c (PIN_OUTPUT | MUX_MODE3) \u00a0\u00a0\/* gpio_155.uart4_rx *\/\r\n\r\n\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a00x11e (PIN_OUTPUT | MUX_MODE3) \u00a0\u00a0\/* gpio_156.uart4_tx *\/\r\n\r\n\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0&gt;;\r\n\r\n\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0};\r\n\r\n\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\r\n\r\n\/* Pinmux for gpios on J6 expansion header *\/\r\n\r\n\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0j6_gpios: pinmux_j6_gpios{\r\n\r\n\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0pinctrl-single,pins = &lt;\r\n\r\n\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a00x10 (PIN_OUTPUT | MUX_MODE3) \u00a0\u00a0\u00a0\/* gpio_32.gpmc_ad8 *\/\r\n\r\n\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a00x12 (PIN_OUTPUT | MUX_MODE3) \u00a0\u00a0\u00a0\/* gpio_33.gpmc_ad9 *\/\r\n\r\n\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a00x14 (PIN_OUTPUT | MUX_MODE3) \u00a0\u00a0\u00a0\/* gpio_34.gpmc_ad10 *\/\r\n\r\n\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a00x16 (PIN_OUTPUT | MUX_MODE3) \u00a0\u00a0\u00a0\/* gpio_35.gpmc_ad11 *\/\r\n\r\n\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a00x18 (PIN_OUTPUT | MUX_MODE3) \u00a0\u00a0\u00a0\/* gpio_36.gpmc_ad12 *\/\r\n\r\n\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a00x1a (PIN_OUTPUT | MUX_MODE3) \u00a0\u00a0\u00a0\/* gpio_37.gpmc_ad13 *\/\r\n\r\n\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a00x1c (PIN_OUTPUT | MUX_MODE3) \u00a0\u00a0\u00a0\/* gpio_38.gpmc_ad14 *\/ \u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\r\n\r\n\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a00x34 (PIN_OUTPUT | MUX_MODE3) \u00a0\u00a0\u00a0\/* gpio_50.gpmc_ncs0 *\/\r\n\r\n\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a00x36 (PIN_OUTPUT | MUX_MODE3) \u00a0\u00a0\u00a0\/* gpio_51.gpmc_ncs1 *\/\r\n\r\n\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a00x3c (PIN_OUTPUT | MUX_MODE3) \u00a0\u00a0\u00a0\/* gpio_54.gpmc_nwp *\/\r\n\r\n\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a00x3e (PIN_OUTPUT | MUX_MODE3) \u00a0\u00a0\u00a0\/* gpio_55.gpmc_clk *\/\r\n\r\n\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a00x40 (PIN_OUTPUT | MUX_MODE3) \u00a0\u00a0\u00a0\/* gpio_56.gpmc_nadv_ale *\/\r\n\r\n\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a00x46 (PIN_OUTPUT | MUX_MODE3) \u00a0\u00a0\u00a0\/* gpio_59.gpmc_nbe0_cle *\/\r\n\r\n\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a00x4a (PIN_OUTPUT | MUX_MODE3) \u00a0\u00a0\u00a0\/* gpio_61.gpmc_wait0 *\/ \u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\r\n\r\n\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\/\/ 0xD4 (PIN_OUTPUT | MUX_MODE3) \u00a0\u00a0\u00a0\/* gpio_121.h_dmtimer11_pwm *\/ \u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\r\n\r\n\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0&gt;;\r\n\r\n\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0};<\/pre>\n<h2><span class=\"ez-toc-section\" id=\"Sources\"><\/span>Sources<span class=\"ez-toc-section-end\"><\/span><\/h2>\n<ul>\n<li><a href=\"http:\/\/www.linux-magazin.de\/Ausgaben\/2013\/06\/Kern-Technik\">http:\/\/www.linux-magazin.de\/Ausgaben\/2013\/06\/Kern-Technik<\/a><\/li>\n<li><\/li>\n<\/ul>\n<h2><span class=\"ez-toc-section\" id=\"Get-in-Touch\"><\/span>Get in Touch<span class=\"ez-toc-section-end\"><\/span><\/h2>\n<p>Are you interested in embedded systems for the internet of things (IoT)? Visit our <a href=\"https:\/\/www.inovex.de\/en\/our-services\/mobile\/internet-of-things-smart-devices\/\" target=\"_blank\" rel=\"noopener\">website<\/a>, write an Email to <a href=\"mailto:list-blog@inovex.de\" target=\"_blank\" rel=\"noopener\">list-blog@inovex.de<\/a> or call\u00a0<a href=\"tel:+497216190210\" target=\"_blank\" rel=\"noopener\">+49 721 619 021-0<\/a>.<\/p>\n","protected":false},"excerpt":{"rendered":"<p>Traditionally, the specific hardware configurations are described in so called board-description files and permanently embedded into the kernel during compilation, making it necessary to re-compile the kernel to change pin assignment.\u00a0The Device Tree is supposed to revolutionize that\u00a0by\u00a0reading the hardware configuration from a data structure stored in RAM at startup. In this article we describe [&hellip;]<\/p>\n","protected":false},"author":35,"featured_media":12345,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"_acf_changed":false,"inline_featured_image":false,"ep_exclude_from_search":false,"footnotes":""},"tags":[74],"service":[712],"coauthors":[{"id":35,"display_name":"Anna-Lena Marx","user_nicename":"amarx"}],"class_list":["post-21006","post","type-post","status-publish","format-standard","has-post-thumbnail","hentry","tag-iot","service-internet-of-things-iot"],"acf":[],"yoast_head":"<!-- This site is optimized with the Yoast SEO plugin v26.5 - https:\/\/yoast.com\/wordpress\/plugins\/seo\/ -->\n<title>Enhancing a Device Tree for ARM CPUs - inovex GmbH<\/title>\n<meta name=\"description\" content=\"The Device Tree is supposed to revolutionize that\u00a0by\u00a0reading the hardware configuration from a data structure stored in RAM at startup.\" \/>\n<meta name=\"robots\" content=\"index, follow, max-snippet:-1, max-image-preview:large, max-video-preview:-1\" \/>\n<link rel=\"canonical\" href=\"https:\/\/www.inovex.de\/de\/blog\/enhancing-a-device-tree-for-arm-cpus\/\" \/>\n<meta property=\"og:locale\" content=\"de_DE\" \/>\n<meta property=\"og:type\" content=\"article\" \/>\n<meta property=\"og:title\" content=\"Enhancing a Device Tree for ARM CPUs - inovex GmbH\" \/>\n<meta property=\"og:description\" content=\"The Device Tree is supposed to revolutionize that\u00a0by\u00a0reading the hardware configuration from a data structure stored in RAM at startup.\" \/>\n<meta property=\"og:url\" content=\"https:\/\/www.inovex.de\/de\/blog\/enhancing-a-device-tree-for-arm-cpus\/\" \/>\n<meta property=\"og:site_name\" content=\"inovex GmbH\" \/>\n<meta property=\"article:publisher\" content=\"https:\/\/www.facebook.com\/inovexde\" \/>\n<meta property=\"article:published_time\" content=\"2015-11-30T12:29:22+00:00\" \/>\n<meta property=\"article:modified_time\" content=\"2025-03-24T06:38:53+00:00\" \/>\n<meta property=\"og:image\" content=\"https:\/\/www.inovex.de\/wp-content\/uploads\/2015\/11\/pandaboard-sensor-android-embedded.jpg\" \/>\n\t<meta property=\"og:image:width\" content=\"2300\" \/>\n\t<meta property=\"og:image:height\" content=\"678\" \/>\n\t<meta property=\"og:image:type\" content=\"image\/jpeg\" \/>\n<meta name=\"author\" content=\"Anna-Lena Marx\" \/>\n<meta name=\"twitter:card\" content=\"summary_large_image\" \/>\n<meta name=\"twitter:image\" content=\"https:\/\/www.inovex.de\/wp-content\/uploads\/2015\/11\/pandaboard-sensor-android-embedded-1024x302.jpg\" \/>\n<meta name=\"twitter:creator\" content=\"@inovexgmbh\" \/>\n<meta name=\"twitter:site\" content=\"@inovexgmbh\" \/>\n<meta name=\"twitter:label1\" content=\"Verfasst von\" \/>\n\t<meta name=\"twitter:data1\" content=\"Anna-Lena Marx\" \/>\n\t<meta name=\"twitter:label2\" content=\"Gesch\u00e4tzte Lesezeit\" \/>\n\t<meta name=\"twitter:data2\" content=\"6\u00a0Minuten\" \/>\n\t<meta name=\"twitter:label3\" content=\"Written by\" \/>\n\t<meta name=\"twitter:data3\" content=\"Anna-Lena Marx\" \/>\n<script type=\"application\/ld+json\" class=\"yoast-schema-graph\">{\"@context\":\"https:\/\/schema.org\",\"@graph\":[{\"@type\":\"Article\",\"@id\":\"https:\/\/www.inovex.de\/de\/blog\/enhancing-a-device-tree-for-arm-cpus\/#article\",\"isPartOf\":{\"@id\":\"https:\/\/www.inovex.de\/de\/blog\/enhancing-a-device-tree-for-arm-cpus\/\"},\"author\":{\"name\":\"Anna-Lena Marx\",\"@id\":\"https:\/\/www.inovex.de\/de\/#\/schema\/person\/b7d6fd8c3ec8972f3b14f0205e25d022\"},\"headline\":\"Enhancing a Device Tree for ARM CPUs\",\"datePublished\":\"2015-11-30T12:29:22+00:00\",\"dateModified\":\"2025-03-24T06:38:53+00:00\",\"mainEntityOfPage\":{\"@id\":\"https:\/\/www.inovex.de\/de\/blog\/enhancing-a-device-tree-for-arm-cpus\/\"},\"wordCount\":844,\"commentCount\":0,\"publisher\":{\"@id\":\"https:\/\/www.inovex.de\/de\/#organization\"},\"image\":{\"@id\":\"https:\/\/www.inovex.de\/de\/blog\/enhancing-a-device-tree-for-arm-cpus\/#primaryimage\"},\"thumbnailUrl\":\"https:\/\/www.inovex.de\/wp-content\/uploads\/2015\/11\/pandaboard-sensor-android-embedded.jpg\",\"keywords\":[\"IoT\"],\"articleSection\":[\"Applications\",\"English Content\",\"General\"],\"inLanguage\":\"de\",\"potentialAction\":[{\"@type\":\"CommentAction\",\"name\":\"Comment\",\"target\":[\"https:\/\/www.inovex.de\/de\/blog\/enhancing-a-device-tree-for-arm-cpus\/#respond\"]}]},{\"@type\":\"WebPage\",\"@id\":\"https:\/\/www.inovex.de\/de\/blog\/enhancing-a-device-tree-for-arm-cpus\/\",\"url\":\"https:\/\/www.inovex.de\/de\/blog\/enhancing-a-device-tree-for-arm-cpus\/\",\"name\":\"Enhancing a Device Tree for ARM CPUs - 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